The present invention relates to a semiconductor device. In particular, it relates to a semiconductor device which is called semiconductor silicon on an insulator, namely SOI (Silicon On Insulator). The semiconductor silicon on the insulator is called SOI hereinafter for simplification.
FIG. 2 shows a cross-sectional structure of a SOI wafer. 21 is a thick single crystal silicon substrate, 22 is a silicon oxide film SiO having a thickness of several hundred .ANG. to several .mu.m, and 23 is a thin single crystal silicon layer having a thickness of several hundred .ANG. to several .mu.m. In the SOI wafer, electric elements such as transistors, resistors, capacitors and the like are formed on the thin single crystal silicon layer 23.
By the way, the present invention relates to a semiconductor device formed on semiconductor single crystal silicon on an electrically insulating substance formed as a layer on the whole face of the thick single crystal silicon substrate 21 using at least a complementary type metal/insulator semiconductor transistor integrated circuit (complementary type MIS transistor). The MIS transistor refers to a transistor of the electric field effect type in which a certain type of insulation film (for example, a silicon nitride film single layer, multiple layers of the silicon nitride film and the silicon oxide film and the like), which is not limited to the silicon oxide film, is used for a gate insulation film. In the following explanation of the present invention, the explanation will be made using the metal/oxide film/semiconductor transistor (MOS transistor) which is most general in the MIS transistor as an example. Even when the MOS transistor is used to explain in the explanation, the MIS transistor is generally described.
FIG. 3 shows a cross-sectional structure of a partial portion of a conventional complementary type MOS integrated circuit (hereinafter referred to as CMOSIC) formed on a SOI wafer. 31 indicates a single crystal silicon substrate, 32 indicates a silicon oxide film (hereinafter abbreviated as BOX (Buried Oxide: abbreviation of the buried oxide film) having a thickness of several hundred .ANG. to several .mu.m, 33 and 34 indicate a source and a drain of an N-type MOS transistor respectively, 35 indicates a gate electrode comprising polycrystalline silicon, 36 indicates a gate insulator comprising a silicon oxide film, and 37 indicates a P well comprising a P-type impurity having a low concentration. The N-type MOS transistor is formed by the source 33, the drain 34, the gate electrode 35, the gate insulator 36 and the P well 37. 38 and 39 indicate a source and a drain of a P-type MOS transistor, 310 indicates a gate electrode comprising polycrystalline silicon, 311 indicates a gate insulation film comprising a silicon oxide film, 312 indicates an N well comprising an N-type impurity having a dilute concentration. The P-type MOS transistor is formed by the source 38, the drain 39, the gate electrode 310, the gate insulator 311 and the N well 312.
In FIG. 3, 313 indicated at three places is a thick silicon oxide SiO.sub.2 for isolation (hereinafter referred to as the field oxide).
In FIG. 3, in the CMOSIC formed on the conventional SOI wafer, the bottoms of the source 33 and the drain 34 of the N-type MOS transistor and the source 38 and the drain 39 of the P-type MOS transistor have contacted with the BOX 32.
FIG. 4 shows distribution of the boron concentration as the P-type impurity for forming the P well in the depth direction of the BOX 32 and the P well on the straight line A--A' shown in FIG. 3.
As clarified from FIG. 4, at the boundary between the BOX 32 and the P well as the single crystal silicon layer, due to the segregation of boron, the concentration of boron rapidly decreases at the side of the single crystal silicon layer. Thus, the region of 314 shown in FIG. 3 contacting with the BOX 32 of the P well 37 has an extremely low concentration of boron, which becomes a region in which a current passage of the N-type MOS transistor is apt to be formed.
Thus, in the N-type MOS transistor of the CMOSIC shown in FIG. 3, a parasitic channel is subject to occur in the region 314, and the leak current will become extremely large.
On the other hand, FIG. 5 shows distribution of the phosphorus concentration as the N-type impurity for forming the N well in the depth direction of the BOX 32 and the N well on the straight line B--B' shown in FIG. 3.
As clarified from FIG. 5, at the boundary between the BOX 32 and the N well as the single crystal silicon layer, due to the segregation of phosphorus, the concentration of phosphorus increases at the side of the single crystal silicon layer. Thus, the concentration of phosphorus is relatively high in the region of 315 shown in FIG. 3 contacting with the BOX 32 of the N well 312, and the current passage is difficult to be formed in this region.
Thus, with respect to the P-type MOS transistor of the MOSIC shown in FIG. 3, it is difficult to generate the parasitic channel in the region 315, and hence the leak current is also small, showing good transistor characteristics.
As explained above, in the CMOSIC formed on the conventional SOI wafer, the bottoms of the source and the drain of the N-type MOS transistor contact with the BOX, so that at the boundary between the P well and the BOX in the N-type transistor, the parasitic channel is formed, the leak current is large, and good transistor characteristics are not obtained. Therefore, as characteristics of the CMOSIC, since the leak current is large, there has been a conventionally experienced drawback in that excellent CMOSIC characteristics, including low electric power consumption, are not obtained.
The present invention is directed to the CMOSIC formed on the SOI wafer, an object of which is to suppress the leak current of the N-type MOS transistor, and consequently obtain excellent characteristics inherent in a CMOSIC having low electric power consumption.
In addition, the thickness of the single crystal silicon layer on the electrically insulating substance in the semiconductor device of the present invention is thicker than the thickness of the single crystal silicon layer on the electrically insulating substance of the conventional structure shown in FIG. 3.
In the conventional semiconductor device having the structure shown in FIG. 3, no single crystal silicon layer is present under the field oxide film 313 as the isolation region, and the isolation between devices existing at both sides of the field oxide film 313 is complete owing to the fact that no current passage is present under the field oxide film.
On the other hand, in the semiconductor device of the present invention, the single crystal silicon layer remains at least under the field oxide film as the isolation region for interposing the region in which the N-type MOS transistor is formed. Thus, as compared with the conventional semiconductor device having the structure shown in FIG. 3, it has a drawback as having the structure in which the isolation is weak.
Thus, it is another object of the present invention to certainly perform the isolation even when the single crystal silicon layer remains in the element isolation region.